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Expert Logic Design Engineer (FPGA/ASIC)

Poland Remote

DCV Technologies

Undisclosed Salary

9 days

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Verification Engineer

Warszawa

Integral Solutions

Undisclosed Salary

7 days

Senior Verification Engineer (UVM/SystemVerilog)

Warsaw

Square One

25 200 PLN/month

23 days

Principal Analog Mixed-Signal IC Design Engineer

Kraków

Blue Origin

Undisclosed Salary

21 days

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FPGA/Digital Lead Engineer

Wrocław

Varion Space

Undisclosed Salary

44 days